1. Field of the Invention
The invention relates generally to sense amplifiers, and more particularly to a sense amplifier having improved speed and noise margin characteristics.
2. Description of Related Art
Sense amplifiers are used in a number of digital circuitry applications to speed-up the transition time between changes in logic levels. For the most part, this is accomplished by compressing input levels to just above or below the switch point of a sensing inverter. The swing or "slew" of the input therefore need not be as large to trigger the inverter to switch logic states. This level "compression" however is not without limitations.
FIG. 1 depicts a typical prior art sense amplifier 10 having an input node 14 coupled to receive logic input signals from an N-channel MOSFET logic tree 12. The input node 14 is coupled to the sources of load P-channel transistor 28 and fast recovery N-channel transistor 36, and to an input on sensing inverter 32. An output on inverter 32 drives the gate of fast recovery transistor 36, an input on feedback inverter 30, and em input on output driver inverter 34. An output on feedback inverter 30 drives the gate of load transistor 28. The drains of load transistor 28 and fast recovery transistor 36 are coupled to the supply voltage V.sub.DD. The output voltage on driver inverter 34 swings substantially between ground and V.sub.DD to restore logic levels to their normal amplitudes.
A limitation with the sense amplifier 10 depicted in FIG. 1 is the magnitude and fall time of the steady state high level on the input to sense inverter 32 (node 14). This point is best illustrated with reference to FIG. 2. At time zero, waveform 44 (which is the gate voltage of one or more of the plurality of transistors in logic tree 12) is depicted as being high thus pulling down the voltage on input node 14 (represented as waveform 46). As waveform 44 is driven low at point 15, logic tree 12 begins to cease sinking current allowing voltage waveform 46 to be pulled up through transistors 28 and 36 to V.sub.DD. As waveform 46 increases and crosses switch point 52 of inverter 32 at point 19, the output of inverter 32 (represented as waveform 48) begins to go low turning off transistor 36 and driving feedback inverter 30 high which turns off load transistor 28. This leaves node 14 in a high impedance state suspect to leakage, reducing the noise margin of the sense amplifier, making operation less reliable.
The output of driver inverter 34 (represented by waveform 50) swings from the negative voltage rail (ground) to substantially the positive voltage rail (V.sub.DD) to restore logic levels to their appropriate magnitude. The steady state input to inverter 32 a.k.a. node 14 (waveform 46) levels off to a variable (depicted as dashed) high level voltage 56 subject to leakage, variations in the switch point 52 of inverter 32, and the variable delay induced by inverters 30 and 32 and transistors 28 and 26, all of which are subject to changes in process technology.
As waveform 44 is driven high at point 17, logic tree 12 begins to sink current through transistors 28 and 36 pulling waveform 46 on input node 14 below switch point 52 of inverter 32 at point 21. Waveform 48 (the output of inverter 32) then begins to go high turning on transistor 36 and driving the output of feedback inverter 30 low which turns on load transistor 28. Also in response to waveform 48 going high, waveform 50 (the output of inverter 34) goes low. The response time it takes output waveform 50 to fully respond to the change in input waveform 44 at point 17 is depicted as t.sub.1.
It can be seen from the foregoing that without jeopardizing noise margin characteristics, it is desirable to reduce the steady state level above the switch point of the sensing inverter thus reducing t.sub.1, to improve the sense amplifier switching speed.